Four quadrant multiplying divider using three log circuits

摘要

Three log circuits are fed by respective x, y and z inputs, along with predetermined interconnections therebetween. The outputs from the log circuits are log z, log (x+z) and log (y+z). These outputs are fed to summing and anti-log circuits to derive the equation (xy)/z + x + y + z. A second summing circuit is provided for substracting the three variables from the resultant output so that (xy)/z is finally derived.