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Adder with fast detection of sum equal to zeroes or radix minus one
Adder with fast detection of sum equal to zeroes or radix minus one
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机译:快速检测到总和等于零或基数减一的加法器
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摘要
Logic circuits in an adder for use in data processing for the detection of a sum of all ZEROES together with the mathematics upon which the circuits are based. Circuits and mathematics are also disclosed for a detection of a sum of all digits equal to the radix less one. Each of these detected sum conditions are produced prior to or at least concurrently with the production of the sum itself.
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