Look ahead controls for address translation operation - provides look ahead feature when segmentation registers are loaded to reduce time needed to select memory units to be accessed

摘要

The look ahead circuits are for an address relocation translator which contains stacks of segmentation registers (SR's), each of which may be loaded with an assigned address of a physical block in a main memory. An additional pair of bit positions are provided with each SR to receive look ahead bits from decoder loading circuits which decode a physical address being loaded into the SR to indicate the storage unit containing the addressed block. During each subsequent address translation the loaded look ahead bits are outgated while the block address is being read from an SR. The look ahead bits are decoded for selecting the required storage unit component of the main memory, and a translator interface is switched to that unit. The look ahead bits are handled by parallel high speed circuits so that the required storage unit is selected before a storage unit cycle is generated by the translator for accessing the addressed block.