ELECTRONIC LOGIC CIRCUIT AND ASEQUENTIAL AND ASYNCHRONOUS CONTROL SYSTEM COMPRISING A PLURALITY OF SUCH LOGIC CIRCUITS

摘要

1466323 Transistor switching and pulse shaping circuits THOMSON-CSF and AGENCE NATIONALE POUR LA VALORISATION DE LA RECHERCHE 4 April 1974 [6 April 1973] 15098/74 Heading H3T A switching circuit for delaying the leading and trailing edges of a pulse by different amounts comprises a capacitor C1 charged through a first resistive path R7, R9, R10 and discharged through a second resistive path R10 to give two different time constants, the assembly being connected between the collector of a first transistor T 5 and a second transistor T 6 acting as a current amplifier and being followed by an output stage T 7 and being fed from a bi-stable 10, 11. When the bi-stable output changes to a logical "0", transistor T 5 is cut off and capacitor C1 charges through resistors R 7 , R 9 , R 10 until transistors T 6 , T 7 switch on to produce a "0" output after a first delay. If the bi-stable output is switched to a "1" level, transistor T 5 is switched on and the capacitor discharges through R 10 until transistors T 6 , T 7 cuts off after a second, different delay to give a "1" output.