1482163 Space charge limited transistors INTERNATIONAL BUSINESS MACHINES CORP 29 Nov 1974 [26 Dec 1973] 51741/74 Heading H1K In operation of a planar space charge limited transistor comprising a high resistivity substrate, emitter and collector regions of one conductivity type extending into it from one surface and a third region of opposite conductivity type extending into said surface between them, the part of the substrate between the emitter and collector regions has a dielectric relaxation time much larger than the carrier transit time, and the third region is separated at least from the emitter by an insulating region extending inwards from said surface in order to reduce bipolar transistor action. As described the substrate has a resistivity of #10,000 ohm cm. and the regions which form abrupt junctions with the substrate a doping of at least 10SP19/SP atoms/c.c., and the insulating region is preferably formed by oxidation through silicon nitride masking following an etching step, though it may alternatively be alumina, silicon nitride, or pyrolytic oxide deposited in an etched groove. In the Fig. 2 embodiment a structure consisting of a pair of complementary devices mutually isolated by P+ and N+ diffused regions 36, 37 can be formed on a common substrate 7 using only two diffusion steps, interconnections being provided by metallization such as 38 disposed over recessed oxide to reduce stray capacitance or by regions common to both devices. In modifications the third region may be of greater or smaller depth than the emitter and collector. Operation is discussed in detail.
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