Data compressor for redundancy elimination - uses shift register and counter controlled by comparison of successive words to direct run length coding station

摘要

A data compression system for data transmission is designed to eliminate any reduncies in bit series. The series of input bits at the transmitter are processed through a run-length-coding station (2) to produce groups of 3 bits that are entered into a six stage shift register (31). The two words in the shift register are compared (32) and if identified a counter (33) is activated (I). Switching stages (4, 5, 6) are controlled (35) to combine the shift register outputs with the counter outputs in a second run-length-coding station (7). If identical the run length coding station produces an output with the redundancy eliminated.