Data multiple processor with coordinated parallel data flows - operates several storage and peripheral channels in parallel taking account of inbuilt priority system

摘要

A digital data multiple processor uses a central co-ordinator unit to control the parallel operation of a number of storage units a number of peripheral control units and a central processor, so that links between these units are established as the programs require taking account of an inbuilt priority system, and so that many operations can proceed in parallel. The processor consists of an array of independent storage units (SP1, SP2...SP4) a central processor (ZP) and a number of indpendent peripheral (PEG1, PEG2) control (EAP1, EAP2) units. These are served by a number of highways (DASP1, ...