Circuit arrangement for the reception-side evaluation of characteristic bits and to the frame synchronisation of a time multiplex system with the aid of a fixedly predetermined synchronization words

摘要

For evaluating identification bits at the receiving end and for the frame alignment of a time-division multiplex system in which a time-division multiplex signal (E) occurs which exhibits an identification bit after in each case p bits and m identification bits for each time-division multiplex frame, of which in each case s identification bits form one alignment word, an alignment device (SE) contains an addressable memory (RAM) with p+1 memory blocks of m-1 storage cells each which is addressed by p+1 addresses from an address generator (AG2) during the occurrence of the individual bits of the time-division multiplex signal (E). A clock generator (TG2) in each case includes the memory (RAM) in a read-in phase and in a read-out phase during the period of the individual bits of the time-division multiplex signal (E). The alignment device (SE) also includes a buffer memory (ZSP1) which is supplied with the time-division multiplex signal (E) in a first memory cell (aa) and which is connected with other memory cells (bb, cc) to outputs and inputs (a, b) of the memory (RAM) and to a decoder (DC). IMAGE