Digital speed control system for vehicles - has registers for acceleration velocity and error functions with trigger control and binary digital interconnections

摘要

The digital speed control system, esp. for a motor vehicle, employs a logic circuit with an acceleration register (12), a counter (14), a movement register (16) and a correction register (18). The circuit is triggered by input through an AND gate (38) and an OR gate (39) and a three-way mode (44) to the T (trigger) input terminal on the registers (12, 14, 18). The movement counter (16) is operated by a coincidence AND gate (32). Connections between the various registers are made on the easier of one line per binary stage for acceleration (A1, A2...A128), velocity (V1, V2...V128), velocity complement (V1, V2...V128), speed (S, S2...S128) and error (E1, E2...E128). The last stage on each of the boundary registers connects to an overflow line (48, 22).