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Mesa semiconductor element with high blocking voltage - has limited impurity gradient near pn-junction and specified depth of mesa groove
Mesa semiconductor element with high blocking voltage - has limited impurity gradient near pn-junction and specified depth of mesa groove
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机译:具有高阻断电压的台面半导体元件-在pn结附近具有指定的台面深度限制的杂质梯度
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摘要
The semiconductor substrate of the mesa component has two main surface (12, 11) which are connected by an end surface (13). In one surface (12) is formed a mesa groove (14) as a closed ring extending towards the second main surface. The groove surrounds a semiconductor region of the one conductivity which forms a pn-junction (Jc) with a region of second conductivity. The gradient of impurity concentration near the pn-junction does not exceed 3.5 x 10I7 atoms /cm4. The mesa groove depth equals at least the some of the pna-junction depth and 10% of the width of a depletion layer, formed by application of an avalanche voltage at the pnj-junction. The groove width is at least three times its depth.
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机译:台面组件的半导体衬底具有两个主表面(12、11),两个主表面通过端面(13)连接。在一个表面(12)中形成作为向第二主表面延伸的闭合环的台面凹槽(14)。凹槽围绕具有一个导电性的半导体区域,该半导体区域形成具有第二导电性的区域的pn结(Jc)。 pn结附近的杂质浓度梯度不超过3.5 x 10I7原子/ cm4。台面凹槽深度至少等于pna结深度的一部分,并且等于耗尽层宽度的10%,该耗尽层宽度是通过在pnj结处施加雪崩电压而形成的。凹槽宽度至少为其深度的三倍。
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