System for rapid division of floating point numbers - applies intermediate corrections during calculation to provide high speed precise division

摘要

The systems has an observation network (1). This network supplies an output signal. That is when the contents of a fourth register (D) equals the number N/n,where n equals the number of bits forming a partial quotient. A first combination network (2) of the system evaluates the logic connection between the contents of a first register (A) and that of a third register (C). The combination network carries out, when the need arises, one or several shifts in a second register (B). This is so as to execute the necessary correction of the quotients characteristic. A second combination network (3) of the system produces an output signal. This output signal, when required, carries out one or several shifts in the fourth register (D). This corrects the number of partial operations still to be carried out in response three electrical signals. That is to the contents of the first register (A). To the output signals of the observation network and of the first combination network (2). This is so that the output signals in question are transmitted to the inputs of the second combination network either immediately or via the central programmed unit of the system.