Negating logic stage for arbitrary pulse patterns - has negatable signal and required output applied to AND-gate, and constant test signal to OR-gate

摘要

The negating logic stage for arbitrary pulse patterns in control circuits has the pulses requiring negating applied to an AND-gate first input. The logic sequence that should appear at the output of an OR-gate is applied to the AND-gate second input. The AND-gate output is coupled to the OR-gate first input. A test signal is continuously applied to the OR-gate second input. Two separate pulse pattern tables may be used. A variation on this basic circuit contains an OR-gate with a third input controlled by a gate. After passing the negating stage the pulse pattern has a correct phase.