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Clock pulse generator for communication systems - has counters stepping down pulse trains, and reset by switches which retransmit pulse

机译:用于通信系统的时钟脉冲发生器-具有计数器来降低脉冲序列,并通过重新发送脉冲的开关进行复位

摘要

An individual electronic counter is allocated as a stepping down stage to each clock pulse train, to which the fundamental frequency is directly applied for its control. Switches are provided in the output, corresp. to a specified number of fundamental cycles. They mark this number of cycles. Or coincidence evaluating electronic switches are connected to the outputs of decadal switches, which mark the specified number of fundamental cycles. Or the counter outputs coding the numbers are connected to coincidence dependent switches, so that during a coincidence a switch becomes operative, resets a counter and retransmits a clock pulse.
机译:单个电子计数器作为降压级分配给每个时钟脉冲序列,基频直接应用到其上进行控制。在输出corresp中提供了开关。到指定数量的基本周期。他们标记了这个循环数。或者将符合性评估电子开关连接到十进制开关的输出,这些开关标记了指定的基本周期数。或将编码数字的计数器输出连接到与重合有关的开关,以便在重合期间开关可操作,重置计数器并重新发送时钟脉冲。

著录项

  • 公开/公告号DE2748828A1

    专利类型

  • 公开/公告日1979-05-03

    原文格式PDF

  • 申请/专利权人 DIRRJOSEFING.;

    申请/专利号DE19772748828

  • 发明设计人 DIRRJOSEFING.;

    申请日1977-10-31

  • 分类号H03K3/00;H03K5/18;H04M19/00;H04M15/16;

  • 国家 DE

  • 入库时间 2022-08-22 19:48:14

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