Frequency-stabilised control generator with synchronisation counter - produces regulating value for output frequency from time difference between count at end of period and following counter result

摘要

The frequency-stabilised control generator is designed so that its output frequency can be set to a given value within a frequency range not much greater than 1 digit of the lowest decade of the frequency counter. The clock frequency is roughly that needed for the digital frequency counter. There is a synchronous or quasisychronous counter. It is employed such that the control signal for the frequency is obtained from the time difference between the count at the end of the count time and the next count.