Shift register latch circuit operable as a D-type edge trigger and counter comprising a plurality of such latch circuits

摘要

A shift register latch circuit consists of a polarity hold latch (1) connected to a set/reset latch (2). The latches can be clocked with separate non-overlapping clock trains (+A, +B and +C) so that automatically generated test patterns can be applied to a scan input (s) to test the circuit. This conforms to the so-called Level Sensitive Scan Design (LSSD) rules. During system operation, the shift register latch circuit operates as a _"D" type edge trigger by connecting the clock input (+ B) of the set/reset latch (2) to the clock (-C) supplied to the polarity hold latch (1). By connecting a number of shift register latches together a Johnson counter can be formed and by clocking all latches with a single oscillator, a series of non-overlapping clock trains can be produced. Implementations of the shift register latch in AND circuits or AND OR INVERT circuits are described.