Digital frequency display circuit for radio receiver - has R-S flip=flop controlling counter that drives display

摘要

The digital frequency indicating circuit, for a ratio receiver, has a settable bistable flip flop (27) to control the count and sisplay cycle. The flip flop's output (Q) is connected to the zero-setting input (26) of a parallel-readout pulse counter (21) and produces a zero-setting signal when in the set state. The flipflop's set input (S) is connected via a differentiator (28) to the output of a gate (12). A second zero-settable counter (20) is used to subtract the IF signal; its count input (19) is connected to the output of the gate and its output (29) to the bistable flipflop's reset input (R).