Up-grading periodic signals - using comparator causing selector logic to block switch to reference register if signal periods lie outside stipulated tolerances

摘要

Circuitry for up-grading periodic signals has a comparator stage for each pair of sequential signal periods. This stage ascertains if the periods match within stipulated tolerances. A selector logic responds as soon as an adjustable number of sequential signal periods is deemed to lie within the tolerances so that all following corresponding signal periods are switched to a reference register as long as they also lie within the stipulated tolerances. A counter in the form of a digital oscillator is connected to this reference register. This counter is fed with the intermediately stored information in the register during the time of the latest received signal periods. The counting rhythm is identical to the signal frequency but is independent w.r.t. phase.