Data transmission clock pulse recovery appts. - has receive terminal with delayed signal and off=line signal comparison and setting counter giving recovered pulse at output

摘要

Circuitry is for recovery of clock pulses from an incoming data transmission so that the clock pulses can be used for synchronising a decoder, esp. applicable to Bi-phase coded transmissions. A passive delay line delays the incoming signal whilst a by-pass path directs an undelayed signal directly to the input of an exclusive OR gate, the delayed input is presented to the other gate input. The gate output operates the set input of a counter and the recovered clock pulse is taken from the output. The delay line comprises two NAND gates (1, 4) and RC circuitry (2, 3, 5, 6). The delayed and undelayed signals are input to an Exclusive OR gate (7) with its output fed to a NAND gate (8) with a feedback from the counter (9). The NAND gate (8) output is used to set the counter (9). The D type Flip Flop (12) delays the incoming data (E) so that it is available at the output (A2) with reconstituted clock pulse and in sync with the clock pulse at the other output (A1).