IGFET with minimum capacitance - has pyramid island structure with insulated gate structure along apex using silicon deposit on sapphire or spinel

摘要

The insulated gate FET is formed using SOS techniques (Silicon on Sapphire or Spinel), for epitaxial layering so that attention can be directed to overlap, and consequently junction capacitance, reduction. The first semiconductor elements (33, 34) for the source zone (34) and drain (33) are formed parallel to the substrate (36) and with a channel zone (35) between them. The source (34) and drain (33) sections have three parts each (33, 33", 33'", 34', 34'") formed down the sides of the channel zone (35) and onto a foot parallel with the substrate (36). The insulated gate section (32) is mounted along the top of the channel (35) and over the first sections (33', 34') of the source and drain, with gate electrode (31). In one example of gate construction, the overlap capacities are of the order of 0.003pF with channel widths of 4 mu m.