Major/minor loop bubble memory with timing loop

摘要

A major/minor loop bubble memory configuration that provides gap free serial access to the data in the minor loops and which maintains the non- volatility of data when subjected to a power-on-off-on sequence. The configuration includes a timing minor loop in combination with the data storage minor loops in the major/minor loop array. The placement of a single timing bubble within the timing loop permits gap free serial access to the data in the remaining storage minor loops.