N-Bit magnitude comparator of free design

摘要

An N-bit magnitude comparator of tree design having a plurality of one- bit magnitude comparators connected to a cascading network with a first stage adapted to receive signals from each pair of the one-bit magnitude comparators and subsequent stages for receiving signals from the preceding stage in the cascade network. The first and every alternate stage thereafter in the cascading circuit comprises means for inverting the signal polarity to the input of that stage so as to achieve one gate delay per circuit.