D:A converter controlled from computer digital memory - by periodic set pulses and delayed reset pulses with delay time proportional to weighting

摘要

The D/A converter is set periodically by a series of set pulses corresponding to the number weighting code and reset by reset pulses following the set pulses and with a delay time proportional to the weighting of the individual set pulses. A number of D/A converters with different addresses can be controlled by a composite code time multiplexed to the converters and containing the set pulses. The converter contains a binary memory and the set-pulse gating circuit is connected to the memory. The advantage lies in using a memory of drum or disc form of a digital computer to control the converter directly.