A ratioless two phase shift register bit constructed in MOS technology in which in order to reduce the chip area occupied by the bit and to improve both the "high" and "low" signals use is made of kick-up capacitors (T9, T10) coupled between the gate and source of enhancement transistors (T7, T8) serving as transfer and store (TAS) gates. The shift register bit further includes first and second sticks of three transistors (T1 to T3 and T4 to T6) with the TAS gates (T7, T8) connected at one side to a junction (10, 12) of the first and second transistors (T1, T2 and T4, T5) of each stick and at the other side either to the centre transistor (T5) of third transistor (T6) of the next stick in the progression of the signal or to an output (Q) which will be connected to the input (D) of the next shift register bit, which input is the gate of the centre transistor (T2) or third transistor (T3) of the first stick in the next shift register bit. The two transistors of each stick to which the data signal is not applied are clocked in antiphase to each other and each TAS gate (T7 and T8) is clocked in phase with the gate of the first transistor in the next stick in the progression of the signal. Conveniently the kick-up capacitors may comprise depletion or enhancement transistors of the same conductivity type as the other transistors or may be fabricated by a double metallisation process. IMAGE
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