Synchronisation control circuit for series bundle transmissions - uses registers connected to multiplexer controlled by local clocked logic circuit to reconstitute digital signal

摘要

The circuit is used for a digital, mode transmission by series packets, with two successive packets being spaced by a 'blank' N shift register are provided, having n series input binary elements. N is three or more and the respective inputs are connected to a transmission line which supplies information in the form of binary elements at a remote clock rhy thm in series by packets. A write control logic circuit receives the clock signal and has N outputs which are each connected to the clock input of a register. A read control logic circuit has an input coupled to the write circuit and another input receiving a local clock signal. The inputs of an output multiplexer are coupled to the register outputs, the control input being coupled to the read circuit with its output supplying rhythm. A resetting detection circuit is used for detecting the absence of transmission and is connected to the read and write circuits.