The time correction circuit comprises a first shift register circuit including two cascade connected shift registers which are driven by a 1 Hz clock pulse and a switch opened and closed to apply an electric signal to the first register circuit. There are provided a first AND gate circuit connected to receive the output from the first register circuit and the signal produced by the operation of the switch, and a second AND gate circuit connected to receive the output from the first AND gate circuit and a 1 Hz clock pulse for producing a 1 Hz clock pulse when the switch is maintained in the closed state for more than 2 seconds. The switch is also connected to the set terminal of a flip-flop circuit having an output terminal connected to the input terminal of a second shift register circuit including two cascade connected shift registers driven by the 1 Hz clock pulse. The output from the flip-flop circuit is applied to the input terminal of a shift register driven by a clock pulse having a frequency of 32 Hz. Upon receiving the output from the second shift register circuit the last mentioned shift register generates an output which resets the respective shift registers of the second shift register circuit and the flip-flop circuit. Further the output from the second flip-flop circuit and the inverted signal of the output from the first AND gate circuit are applied to a third AND gate circuit for producing a pulse when the switch is maintained closed for less than 2 seconds and then opened.
展开▼
