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INFORMATION PROCESSING SYSTEM IMPLEMENTING PROGRAM STRUCTURES COMMON TO HIGHER LEVEL PROGRAM LANGUAGES

机译:信息处理系统,用于实现高级程序语言所通用的程序结构

摘要

1339284 Digital computers BURROUGHS CORP 28 Nov 1970 [28 Nov 1969] 54199/70 Heading G4A A digital electric information processing system includes main storage means containing operands and descriptors for addressing those operands and a processor adapted to execute an instruction string. The processor includes a first buffer register adapted to receive, from the storage means, address stack descriptors for addressing operands requested by the instruction string, a second buffer register adapted to receive, from the storage means, the operands indicated by the descriptors, and means responsive to the instruction string and adapted to determine whether a descriptor requested by the string is present in the first register and, if not, to fetch it and the corresponding operand from the storage means and to insert them in the respective registers thereby to update the registers. A descriptor is defined as a word containing three information sets or expressions. Access attributes defining protection capability and specifying whether an element referenced in memory can be stored or fetched; interpreter attributes defining the characteristics of the referenced element and a structure expression containing the type of structure within which the element resides. The digital electric information processing system is adapted to implement functions common to many high level programming languages e.g. Fortran, Cobol, Algol, PLI. It is stated that this enables instructions to be evaluated faster. Specifications 1,339,285 and 1,336,981 also referred to. The system.-This comprises a number of processors 10, memory modules 11, peripheral units 19, and a core or disc back-up memory 14, all of the units being mutually connectible. The memory 11 is a free field memory and is further described in Specification 1,336,981. Each processor is controlled by a master control program and provides automatic memory protection, responds to interrupts, and regulates time sharing with the other processors. It includes a buffer holding frequently accessed items to minimize fetches from memory 11. Program operation.-The instructions are nested, i.e. in loops and branches and the program is executed in strings which correspond to the various branches. A buffer 40 is divided into five areas; co-routine control field buffer, name stack buffers, descriptor buffers, resource stack buffers and display buffers and an associative memory. Structure descriptors relating to a program are held in buffer 40 and are referred to as the co-routine control field, and associative memory 41 contains the level 1 address of each descriptor contained in the buffer in order that each up-dated descriptor can be restored quickly to level-1 storage.
机译:1339284数字计算机BURROUGHS CORP 1970年11月28日[1969年11月28日] 54199/70标题G4A数字电子信息处理系统包括主存储装置,该主存储装置包含操作数和用于寻址这些操作数的描述符,以及适用于执行指令字符串的处理器。该处理器包括:第一缓冲器寄存器,其适于从存储装置接收用于寻址指令串所请求的操作数的地址堆栈描述符;第二缓冲器寄存器,其适于从存储装置接收由描述符所指示的操作数;以及装置响应于指令串,并适于确定在第一寄存器中是否存在该串所请求的描述符,如果不存在,则从存储装置中获取该描述符和相应的操作数,并将它们插入相应的寄存器中,从而更新该寄存器。寄存器。描述符定义为包含三个信息集或表达式的单词。访问属性,用于定义保护功能并指定是否可以存储或获取内存中引用的元素;解释器属性,这些属性定义了所引用元素的特征以及包含该元素所驻留的结构类型的结构表达式。该数字电子信息处理系统适合于实现许多高级编程语言(例如,编程语言)所共有的功能。 Fortran,Cobol,Algol,PLI。据指出,这使得指令可以更快地被评估。规格1339285和1336981也被提及。该系统包括多个处理器10,存储器模块11,外围单元19以及核心或磁盘备份存储器14,所有这些单元都是可相互连接的。存储器11是自由场存储器,并且在规范1,336,981中进一步描述。每个处理器均由一个主控制程序控制,并提供自动内存保护,响应中断并调节与其他处理器的时间共享。它包括一个缓冲区,该缓冲区保存经常访问的项目,以最大程度地减少从存储器11的取回。程序操作-指令被嵌套,即在循环和分支中,并且程序以与各个分支相对应的字符串执行。缓冲器40被分成五个区域。协同例程控制字段缓冲区,名称堆栈缓冲区,描述符缓冲区,资源堆栈缓冲区和显示缓冲区以及关联内存。与程序相关的结构描述符保存在缓冲区40中,并称为协同例程控制字段,并且关联存储器41包含缓冲区中包含的每个描述符的1级地址,以便可以恢复每个更新的描述符快速升级到1级存储。

著录项

  • 公开/公告号JPS5740530B1

    专利类型

  • 公开/公告日1982-08-28

    原文格式PDF

  • 申请/专利权人

    申请/专利号JP19700101399

  • 发明设计人

    申请日1970-11-14

  • 分类号G06F9/06;

  • 国家 JP

  • 入库时间 2022-08-22 14:04:00

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