MICROPROGRAMMED COMPUTER CONTROL UNIT CAPABLE OF EFFICIENTLY EXECUTING A LARGE REPERTOIRE OF INSTRUCTIONS FOR A HIGH PERFORMANCE DATA PROCESSING UNIT

摘要

Abstract of the DisclosureA cache oriented pipeline data processing unit includes an executionunit, apparatus for fetching data and instructions, hardware decoder andsequencing circuits and a microprogrammed control unit. The microprogrammedcontrol unit includes first and second control stores. The first controlstore includes a plurality of storage locations, each location for storing atleast an address field and a control sequence field for each of the programinstructions required to be executed by the data processing unit. The controlsequence field is coded to designate which one of a group of hardware controlsequences is to be executed by the hardware sequencing circuits for matchingthe performance of the execution unit and fetching apparatus. The secondcontrol store includes a plurality of groups of storage locations, each groupfor storing the microinstructions required for executing at least a portion ofa program instruction. The microprogrammed control unit in response to eachinstruction op-code reads out signals corresponding to a control sequencefield which are decoded to condition the hardware sequencing circuits forperforming those operations required for execution of the instruction. Thestarting location in the second control store is referenced at the end of thedesignated hardware sequence and instruction execution proceeds under micro-program control.