Decoder with gates and series connected holding circuits - has specified number of word decoding gates or bit decoding gates for given number of columns and rows of memory matrix

摘要

The holding circuits, series connected behind the decoder gates, hold each decoder output at a defined output potential. For n columns, or lines of a memory matrix are provided only n/2 word decoder gates, or bit decoder gates. To each decoder gate (1) are allocated two holding circuits (2), for whose decoding the freed addresses are used as word selection cycles. On each chip, a shaft for wiring of the holding circuits is kept free behind each decoder gate. Preferably, the holding circuit consists of a fully dynamically operating inverter for the decoded signal, several switching transistors energised by a word selection cycle (WA1,WA2), and a holding transistor between the switching transistor output and earth. The gate electrodes of the holding transistors are linked to the inverter output via a common line.