Microprocessor configuration, preferably for the application in multimicroprocessor systems

摘要

This is intended for use in multi-microprocessor systems, particularly for an operating and service processor for EDP systems. Essentially, it consists of a CPU (1) which is connected to I/O circuits (5...9) and a ROM (10) via an internal data (2) and address bus (3). The internal data bus (2) is followed by further bus lines (12) via coupling stages (11, 20), and by the data lines (21) of the external bus system. The further bus lines (12) are connected to a RAM (13), control registers (14, 15), a bus address register (16) and error register (18), and these are connected to inputs of one of the I/O circuits (9). Other features are related to decoding circuits (22, 23, 24), a master request circuit (28), a switching circuit (29), a wait signal circuit (4) and a sequence control circuit (30) and to connections of the control (32) and address lines (27) of the external bus system to switching means of the configuration. IMAGE