Digital processor for real-time signal processing - uses microprograms to configure interconnection of arithmetic and multiplier units with waveform generator

摘要

A processing module (100) communicates with other modules through an interconnection bus (81) and uses a systems bus (85). Internal bus systems (A,B) utilise a pipeline structure format. An arithmetic unit (115) operates on 24 bits while a fast multiplier (120) multiples two 16 bit inputs to provide a 24 bit output. A shift register (130) provides linear interpolation in conjunction with the arithmetic and multiplier units. A function memory (140) contains samples of waveforms to be generated while a data memory (150) contains processed data and addresses for the function memory. An address memory (160) operating sequentially, allows access to the data memory. A memory contains microprograms containing instructions for the interconnection of the units including the waveform memory to obtain a particular processing configuration.