Interface for packet and PCM mode transmission link - uses FIFO buffer memory with write and read control circuits ensuring synchronisation with local clock

摘要

A FIFO memory (9) stores data received in the packet mode. A series parallel register (20) upstream of it allows the data to be received in a serial mode. The register is clocked from a clock recovery circuit (21) which also clocks a shift control circuit (10) at the input to a counter (26). The counter contents are loaded into a buffer memory (25). An envelope detector (27) senses presence or absence of packet data and the number of octets in the packet data read into the buffer is used to address a ROM (33). This issues a gating signal (DOC) for an AND gate (31) to enable the read shift control circuit for the packet data buffer memory. A sequencer (15) issues the respective clock signals for the interface operation.