Method of and apparatus for signaling the end points of the ramp- down interval in a dual ramp analog to digital converter

摘要

In an integrated circuit type dual ramp analog to digital converter (10), the duration of the reference voltage integration, or ramp-down period, is precisely determined to control count accumulation in an external output counter (32a) operating in parallel with the standard internal counter of the integrated circuit. A reference voltage is stored on a flying capacitor (50) that is polarity switched, depending upon the polarity of the input signal, to be applied to the input of an integrator (12) during the ramp-down period. To establish the beginning and end of ramp-down, one end (52) of the flying capacitor (50) is applied to a comparator (54). As the voltage at the monitored end of the flying capacitor (50) undergoes abrupt level changes at the end points of the ramp-down interval, the comparator (54) generates start and stop pulses to the external output counter (32a).