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BUS TROUBLE DETECTION SYSTEM OF BUS LOOP SYSTEM

机译:总线环系统的总线故障检测系统

摘要

PURPOSE:To detect a trouble occurring position by switching control from an act system bus to which trouble occurs to a stand-by bus system and then sending data in specific pattern to the trouble system bus. CONSTITUTION:If the trouble occurs between (x) and (y) on the bus system 0, bus controllers BC1 and BC2 once receiving a signal A from a central bus controller CBU, return an answer signal B to the controller CBU by using a 1- system bus. The controller CBU when receiving the signal B sends a trouble detection start signal C to the controllers BC1 and BC2 and also sends a detection signal D to a 0-system output side, and the detection signal D is supervised on the input system of the system 0 for a time T. The controller BC1 and BC2 once recognizing the signal C sends the signals D to respective output sides of the system 0 and the signal D is supervised on the input side of the system 0 for a time T. Then, the controllers BC1 and BC2 recognize the signal D of the 0-system bus and reset a timer T. In this case, the signal D of the controller BC2 is not recognized within the time T because of the trouble between (x) and (y). That is reported to the controller CBU through the 1-system bus and the controller CBU recognizes the trouble between (x) and (y) on the 0-system bus.
机译:目的:通过将控制从发生故障的行为系统总线切换到备用总线系统,然后以特定模式将数据发送到故障系统总线来检测故障发生位置。组成:如果在总线系统0的(x)和(y)之间发生故障,则总线控制器BC1和BC2一旦从中央总线控制器CBU接收到信号A,请使用1将应答信号B返回至控制器CBU -系统总线。控制器CBU在接收到信号B时向控制器BC1和BC2发送故障检测开始信号C,并且还向0系统输出侧发送检测信号D,并且在系统的输入系统上对检测信号D进行监督。 0持续时间T。控制器BC1和BC2一旦识别出信号C,就将信号D发送到系统0的各个输出侧,并且信号D在系统0的输入侧受到监督,持续时间T。控制器BC1和BC2识别0系统总线的信号D并重置计时器T。在这种情况下,由于(x)和(y)之间的故障,在时间T内无法识别控制器BC2的信号D。 。通过1系统总线将其报告给控制器CBU,并且控制器CBU识别0系统总线上的(x)和(y)之间的故障。

著录项

  • 公开/公告号JPS59127447A

    专利类型

  • 公开/公告日1984-07-23

    原文格式PDF

  • 申请/专利权人 NIPPON DENKI KK;

    申请/专利号JP19830002101

  • 发明设计人 MATSUZAKI MASAYUKI;

    申请日1983-01-10

  • 分类号H04L1/22;G06F13/00;H04L12/42;

  • 国家 JP

  • 入库时间 2022-08-22 09:39:24

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