PURPOSE:To reduce the delay of a timepiece at regulation time as much as possible through simple circuit constitution by resetting a frequency dividing circuit, a second timer circuit, and a minute timer circuit to zero by the output of a regulating circuit, and presetting an hour timer circuit to a value set in an hour presetting circuit. CONSTITUTION:When a display part 46 changes from ''06:59:49'' to ''06:59:50'', the output of a gate circuit 47 goes up to a level H to put the regulating circuit 14 and a receiver control circuit 13 in operation. When the receiver control circuit 13 enters an operation state, a timer- casting receiver 12 is powered on to start broadcasting. A broadcast from a time-casting receiver 12 is received to confirm a time-casting signal consisting of a preannouncement and a correct time signal from the broadcast contents, and a timer signal extracting circuit 11 extracts a correct-time signal of ''07:00:00''. The regulating circuit 14 regulates the timepiece by signals from a gate circuit 47 and time signal extracting circuit 11. A correct time regulating signal of ''07:00:00'' is generated to preset the hour timer circuit 28, a 10-minute timer circuit 26, a 1-minute timer circuit 24, the second timer circuit 22, and frequency dividing circuit 21. At this time, the hour timer circuit 28 is preset to 07, and the 10-minute timer circuit 26, 1-minute timer circuit 24, second timer circuit, and frequency dividing circuit 21 are all set to 00. Namely, the timepiece B is preset to ''07:00:00'' by the correct-time regulating signal of ''07:00:00''.
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