COMBINED USE OF PN SEQUENCE FOR DATA SCRAMBLING AND FRAME SYNCHRONIZATION IN DIGITAL COMMUNICATION SYSTEMS

摘要

ABSTRACTIn a communication system containing a scheme forexternally synchconizing and scrambling digital data signals,serial digital data signals to be transmitted are subdividedinto prescribed numbers or sets between which additional oroverhead bits are inserted, the resulting sequence being summedin a modulo-two adder with a multi-bit maximal length PNsequence so that one of the overhead bits is one of the bits ofthe maximal length scrambling sequence.To mark the beginning of a frame of data, one of thepossible code states of the multi-bit sequence is selected.The multiplexing operation is such that the data rate isincreased by a prescribed factor relative to the original datarate to provide for the insertions of the overhead bits withoutloss of data. The resulting higher data rate sequence is thenmodulo-two added with the output of a scrambler andtransmitted. The resulting scrambled data sequence containsthe multi-bit bit PN framing sequence inserted in sync bitpositions exactly where required. Advantageously, with thisscrambling technique, since each unique state of the framing secorresponds to only one state of the scrambling sequence, thereceiver station can proceed to descramble the receivedscrambled sequence by observing the state of the receivedframing sequence.In order to recover the framing sequence and descramblethe data at the receiver station, the incoming scrambled data-48-sequence is initially applied to timing recovery circuitrywhich derives a clock signal synchronized with the receiveddata signal and bit-synchronizes the data and the clock. Framesynchronization is begun by loading a plurality of receivedscrambled data bits at preselected intervals into a shiftregister that forms pact of a local framing sequence generator.This shift register is clocked at a prescribed fraction of thefrequency of the clock derived from the received data sequence.If the clock is in phase with the bit positions of theframing sequence, the shift register will be loaded withsuccessive bits of the framing sequence and the local framingsequence generator will therefore be capable of generating a PNsequence identical to and in phase with the transmitted framingsequence. If the chosen sequence of bits does not belong tothe framing sequence, the output of the scrambling sequencegenerator will be out of phase with the framing sequence. Whenthis occurs the clocking of the shift register is inhibited byone pulse and the incoming data stream is effectively caused tobe shifted or displaced by one bit position, and the aboveprocess is repeated as necessary until eventually the framingsequence is located and the local framing sequence generator isin phase with the framing sequence. At this time, the stagesof a separate shift register, which forms part of a descrambledPN sequence generator, are forced to the state coincident withthe frame marker. This separate shift register is clocked atthe incoming data rate by the recovered clock and is output ismodulo-two added with the incoming digital data stream, thereby-49-recovering the original multiplexed data with the originalzeros inserted at the framing bit positions.To recover the original data stream, the descrambledsequence is applied to a demultiplexer which effectivelydeletes every overhead bit and outputs the original data at theoriginal data rate.-50-