Circuit solution for the unrestriced use of peripheral chips of the Z80 family of microprocessors by ZILOG over the entire directly addressable input/output range

摘要

For this purpose, it is necessary to achieve parallel processing of the end acknowledgement in asynchronous processes in the vector interrupt since otherwise, due to transit times through the existing daisy-chain lines of the physical priority chain, the input/output chips would result in these systems being blocked if more than four of the family are present. A fixed decoder circuit is used in order to supply the input/output units temporarily with a signal in parallel with the programmed termination, namely RETI (return from maskable interrupt). This bypasses the delay due to the priority chain provided by the manufacturer, and the transit delays produced by the serial data run are reduced to exactly one chip-specific transit time.