Shift register latch circuit means for check and test purposes and contained in LSI circuitry conforming to level sensitive scan design (LSSD) rules and techniques

摘要

LSI circuitry conforming to LSSD rules and techniques usually requires at least a small portion of circuitry used only for check and test purposes. The disclosed circuitry meets the LSSD design rules and techniques and considerably reduces the test circuit overhead. The disclosure modifies the known shift register latch (SRL) strategy by replacing the SRL's by master latches in such a manner that the information contained in them is shifted in cascades, using the "division by two" principle for the master latches on the chip. The shift chain having only master latches is selected in response to shift clock signals. By consecutively shifting the respective cascade element, detailed information is obtained for all the master latches on the chip (without the information of the master latches temporarily used as slave latches during shifting) being lost in the cascade element. Level Sensitive Scan Design Rules and Techniques are extensively disclosed in the testing art. See for example: (1) U.S. Pat. No. 3,783,254 entitled "Level Sensitive Logic System" filed Oct. 16, 1972, granted Jan. 1, 1974 to E. B. Eichelberger, of common assignee herewith; or (2) "A Logic Design Structure for LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Ahtomation Conference Proceedings, pp. 462-468, June 20, 21 and 22, 1977, New Orleans, Louisiana, IEEE Catalog Number 77, CH1216-1C.