Differential digital modulation and demodulation system with an analog signal-dependent sampling clock

摘要

A differential digital modulation and demodulation system with an analog signal-dependent sampling clock has a sampling clock-controlled first digital modulator and a predictably functioning second digital modulator, an analog signal to be converted to a digital signal being supplied to both modulators. A control signal for the sampling clock generator for the first digital modulator is generated from a tracking error signal of the second digital modulator, so that the clock frequency of the first digital modulator is increased upon an increasing tracking error and is decreased upon a decreasing tracking error. For digital signal transmission or storage, the digital signal bits are emitted by the modulator and received by the demodulator in the form of signal blocks which include a bit group indicating the respective sampling clock frequency in encoded form. Only one signal block indicating the pause length in encoded form is emitted or received for a particular analog signal pause.