METHOD FOR TESTING INNER SYSTEM OF CONNECTION AMONGST N NUMBER OF OUTPUT OF AN ELECTRIC NETWORK AND DEVICE FOR IMPLEMENTING THIS METHOD, AS WELL AS CIRCUIT ARRANGEMENT FOR TESTING INNER STRUCTURE OF CONNECTION OF THE NETWORKS CONTAINING SEVERAL NODAL POINTS

摘要

PCT No. PCT/HU83/00056 Sec. 371 Date Jun. 15, 1984 Sec. 102(e) Date Jun. 15, 1984 PCT Filed Nov. 15, 1983 PCT Pub. No. WO84/02015 PCT Pub. Date May 24, 1984.A method for the examination of an internal interconnection system between n terminals of an electrical network and for storing the results in a memory comprising n memory cells by means of measuring the existence or non-existence of the signal passage between the terminals, in which a demultiplexer is used to pass a marking state on a terminal of the network and a multiplexer is used to detect the throughpass of the marking signal to other terminals of the network in first cycles a, and when such passage is detected, the positions of the demultiplexer and the multiplexer are stored together with a so called closing bit representing the end of a series of interconnections, and in subsequent cycles b the next undetected terminal is determined which is followed by a next cycle a, and this sequence is continued until all interconnections of the network get stored in the memory. In the apparatus for carrying out the method a first address generator (DMC) is associated with the demultiplexer (DMPX) and a second one (MPC) with the multiplexer (MPX), and a memory (MEM) is used to set the multiplexer. The setting of the multiplexer is temporarily stored in a register (REG) which is subsequently read in the memory. The memory sets the demultiplexer to the selected terminals. The memory setting is facilitated by a memory addressing circuit (MEC). The apparatus is designed to function in accordance with the method and comprises a pair of comparators storing threshold values used for the logical minimizing operations defining the actual fresh memory addresses.