CHARGE REDISTRIBUTION MU-LAW PCM DECODERAbstract of DisclosureA mu-law PCM decoder requiring a total capacitance of only32 times the normalized capacitance Co of the smallest capacitorthereof. The decoder comprises a source of positive and negativereference voltages, a differential input operational amplifierhaving its non-inverting input connected to ground, a storagecapacitor CO=16Co connected as a feedback capacitor between theinverting input and the output terminals of the amplifier so thatthey operate as a voltage source, binary weighted capacitors Cl=Co,C2-2Co, C3=4Co and C4=8Co, and a second unit weighted capacitorC5=Co. Switch means alternately connect one and other sides ofC1-C5 (1) between ground and either a + reference voltage or ground,in accordance with the characterizations in a PCM coded digitalinput word, and (2? across the storage capacitor CO forredistributing charge on the capacitors for each segment of thedesignated polarity. The resultant analog signal established on COin the eighth segment is sampled prior to resetting the chargevoltage on CO to substantially zero volts and receipt of the nextPCM input word. Connections of plates of integrated capacitors andelectrodes of switching transistors to ground and terminals ofvoltage sources renders the decoder substantially insensitive tostray and parasitic capacitance effects associated with theintegrated capacitors and switches.
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