Served as the random selection procedure and choose Shimo-type circuit OSU

摘要

This invention relates to the CMOS type circuit for synchronous, random and sequential selection. The circuit conducts the random selection by a binary counter and a binary decoder composed of n switches (S1-Sn and a n flip-flop (FF1-FFn, and the sequential selection by clock pulse. The input terminals (C2-Cn of flip-flop consists of inverters (V1-Vn-1) and NAND gates (N-Nn-1). The circuit can select the random and sequential selection, conveniently, and reduces the current consumption by using the pulses with a narrow width.