APPARATUS FOR TESTING DYNAMICAL NOISE IMMUNITY OF DIGITAL INTEGRATED CIRCUITS

摘要

Apparatus for testing dynamic noise immunity of digital integrated circuits wherein noise pulses of predetermined duration and amplitude are applied to the inputs of an integrated circuit under test. The tested circuit outputs which normally are at logic level 0 are connected to the inputs of a first group of control logic gates, while the tested circuit outputs which normally are at logic level 1 are connected to the inputs of a second group of control logic gates. The outputs of such groups feed a fault detection circuit. The input voltage thresholds of control logic gates is adjusted by suitable circuits so as to check the dynamic noise immunity of the integrated circuit under test for a predetermined logic swing.