PLA-Based finite state machine with two-level control timing and same- cycle decision-making capability

摘要

A PLA (e.g., 100) operates with two-level clock control timing, that is, with a pair of master and slave registers (e.g., 12 and 13) connected to the PLA wordlines (e.g., W.sub.1, W.sub.2, . . . W.sub.n) between the PLA's AND and OR planes (e.g., 11 and 14). The slave register's output to the OR plane is controlled by a combinational logic device (e.g., 21), such as an AND gate to which a WAIT signal is applied. In this way, when the WAIT signal (e.g., W) is available at the beginning of a given cycle of the clock control timing, the output of the PLA (including PLA feedback) can respond to this WAIT signal before the end of the given cycle--that is, the PLA is capable of same-cycle decision making.