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High speed low power MOS buffer circuit for converting TTL logic signal levels to MOS logic signal levels
High speed low power MOS buffer circuit for converting TTL logic signal levels to MOS logic signal levels
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机译:高速低功耗MOS缓冲电路,用于将TTL逻辑信号电平转换为MOS逻辑信号电平
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摘要
MOS semiconductor address buffer for converting TTL logic states to a MOS logic state requiring only a single clock and having improved power efficiency. The address buffer operates in response to the single clock pulse to set a latch and connect the latch to output drives for providing complementary MOS logic levels.
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