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Simulator system for logic design validation
Simulator system for logic design validation
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机译:用于逻辑设计验证的仿真器系统
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摘要
A hardware network or system is disclosed for testing LSI and VLSI logic device design and system design by simulation utilizing individual gate functions. The simulator system uses switching logic, random access memory, and a state table device to simulate particular test routines to test device design with functions which may appear in random or semi- random sequence.
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