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INEFFECTIVE SYSTEM FOR ADDRESS CONVERSION BUFFER

机译:地址转换缓冲区的无效系统

摘要

PURPOSE:To speed up the ineffectiveness of address conversion buffer, by providing the effective bit in spare set for the effectiveness only to the correspondence to the address conversion pair belonging to the common segment. CONSTITUTION:Spare effective bits 210-213 are provided in correspondence with the effective bits 220 and 221 indicating the effectiveness of the address conversion pair in the address conversion buffer 270. Further, in registrating the address conversion information to the address conversion pair, when the address belongs to the common segment 111 in commonly possession with the address spaces different in the address, the effective bits 220 and 221 and also spare effective bits 210-213 are set. Further, among the address conversion information registrated in the buffer 270, to the instruction of ineffectiveness other than the information belonging to the common segment 111, the spare effective bits 211-213 are used as the effective bits.
机译:目的:通过在备用集中仅将有效位提供给属于公共段的地址转换对的对应关系,以加快地址转换缓冲区的无效性。构成:与有效位220和221相对应地提供了备用有效位210-213,该有效位220和221指示地址转换对在地址转换缓冲器270中的有效性。此外,在将地址转换信息注册到地址转换对时,如果该地址属于公共段111,并且该公共段111的地址空间在地址中不同,则设置有效位220和221以及备用有效位210-213。此外,在缓存器270中登记的地址转换信息中,除了属于公共段111的信息之外,对于无效指令,将备用有效位211-213用作有效位。

著录项

  • 公开/公告号JPS6112583B2

    专利类型

  • 公开/公告日1986-04-09

    原文格式PDF

  • 申请/专利权人 NIPPON ELECTRIC CO;

    申请/专利号JP19780131039

  • 发明设计人 OOMORI JUZO;

    申请日1978-10-26

  • 分类号G06F12/10;

  • 国家 JP

  • 入库时间 2022-08-22 07:49:37

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