LEFT MARGIN SETTING CIRCUIT

摘要

PURPOSE:To make it possible to set the left margin with the precision of the least dot diameter by providing a stop signal generating circuit for transiently stopping generation of load pulses loading parallel data to a shaft register for P/S conversion. CONSTITUTION:A line start synchronizing signal LSYN is detected by a horizon tal synchronizing detector 21. In timing with the immediately following driving clock VCLK, a preset signal is transmitted to a left margin setting counter CT22 for setting the initial value. The CT22 counts VCLK and, when it reaches a preset value, sets a signal A to an H level. The P/S conversion shift register SR25 loads parallel signals by a load signal from a load pulse generating circuit 24. At a preset value before generation of the signal A, the CT22 transmits signals to a weight timing generating circuit 23 to stop the operation of the circuit 24 for a moment to set a loading state for SR25 (shift register). A CT22 releases the stop signal for the circuit 23 before one VCLK of the signal to output serial data from the SR25 to output a printout data WVDO via AND circuit.