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摘要

In a data processing device which consists of a plurality of parallel-operating modules, each of the four modules is provided with its own clock circuit. Synchronization is realized at the level of the cycle of the high frequency oscillation. This is realized in that each of the clock circuits includes a two-out-of-three majority decision device which is fed by the output clock signals of the other three clock circuits. The majority decision may have a simple logic structure and is connected to the actual clock function generator in order to reduce, using a readjustment circuit, the deviation between the clock function signal and the majority signal by a factor substantially smaller than one for each transition of the majority signal.