首页> 外国专利> Circuit arrangement for the instruction-dependent calculation of operand addresses and for checking the page boundary crossing at operands for logical or decimal storage-to-storage instructions

Circuit arrangement for the instruction-dependent calculation of operand addresses and for checking the page boundary crossing at operands for logical or decimal storage-to-storage instructions

机译:用于根据指令计算操作数地址并检查逻辑或十进制存储到存储指令的操作数的页面边界交叉的电路布置

摘要

1. Circuit arrangement for the instruction-dependent calculation of operand addresses and for checking the page boundary crossing at operands for logical or decimal storage-to-storage instructions in a data processing system with a storage system subdivided into pages of equal size, using an address arithmetic unit which, by summation of base address and displacement address and the field length of the first and second operand respectively in each case, signals with the aid of a carry occurring from the most significant bit position of the displacement address part a page boundary crossing of the corresponding operand, characterized in that the address arithmetic unit consists of three sub-adding units, which are linked to one another as follows : a) a main address adder (AAD), forming the first sub-adding unit, is connected via a first and second input register (RA, RB) with associated first and second input multiplexer (MUX A, MUX B) on the one hand to a register set (RS), containing the base or index addresses (B1, B2, X2) of the individual operands, and on the other hand to an instruction buffer for feeding of the associated displacement address (D1, D2) ; b) as second sub-adding unit, a displacement/length adder (DL-ADD) is provided, to the two inputs of which the respectively associated displacement addresses (D1, D2) and operand lengths (L, L1, L2) are fed from the instruction buffer and the output of which is linked via a further input of the second input multiplexer (MUX B) to the second input register (RB) of the first sub-adding unit ; c) the third sub-adding unit is a field-length adder/subtracter (FE-ADD), which is connected by its first input to the output of the first sub-adding unit (AAD), to the second input of which the operand length (L, L1, L2) is fed from the instruction buffer and at the carry output of which a control signal (CY), occurring in the event of a page boundary crossing, can be picked off.
机译:1.电路布置,用于在数据处理系统中将逻辑数或十进制存储到存储的指令划分为相等大小的页面,使用地址算术单元,通过分别求和基址和位移地址以及第一和第二操作数的字段长度的总和,借助于进位信号从位移地址部分的最高有效位出现页边界对应的操作数的相交,其特征在于地址算术单元由三个子加法单元组成,它们相互链接如下:a)连接形成第一子加法单元的主地址加法器(AAD)通过第一和第二输入寄存器(RA,RB)与相关的第一和第二输入多路复用器(MUX A,MUX B)一方面到达寄存器集(RS)各个操作数的基地址或索引地址(B1,B2,X2),另一方面,到达指令缓冲区以馈送相关​​的位移地址(D1,D2); b)作为第二个子加法单元,提供了一个位移/长度加法器(DL-ADD),两个相关的位移地址(D1,D2)和操作数长度(L,L1,L2)被馈送到两个输入指令缓冲器的输出通过第二输入多路复用器(MUX B)的另一输入链接到第一子加法单元的第二输入寄存器(RB)。 c)第三子加法单元是一个场长加法器/减法器(FE-ADD),通过其第一输入连接到第一子加法单元(AAD)的输出,第二子加法器操作数长度(L,L1,L2)从指令缓冲区馈送,并且在其进位输出处,可以拾取发生页边界交叉时出现的控制信号(CY)。

著录项

  • 公开/公告号EP0175997A1

    专利类型

  • 公开/公告日1986-04-02

    原文格式PDF

  • 申请/专利权人 SIEMENS AKTIENGESELLSCHAFT;

    申请/专利号EP19850111428

  • 发明设计人 KOHLER MANFRED DIPL.-ING.;

    申请日1985-09-10

  • 分类号G06F9/34;G06F12/04;

  • 国家 EP

  • 入库时间 2022-08-22 07:35:31

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