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Circuit arrangement for the instruction-dependent calculation of operand addresses and for checking the page boundary crossing at operands for logical or decimal storage-to-storage instructions
Circuit arrangement for the instruction-dependent calculation of operand addresses and for checking the page boundary crossing at operands for logical or decimal storage-to-storage instructions
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机译:用于根据指令计算操作数地址并检查逻辑或十进制存储到存储指令的操作数的页面边界交叉的电路布置
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摘要
1. Circuit arrangement for the instruction-dependent calculation of operand addresses and for checking the page boundary crossing at operands for logical or decimal storage-to-storage instructions in a data processing system with a storage system subdivided into pages of equal size, using an address arithmetic unit which, by summation of base address and displacement address and the field length of the first and second operand respectively in each case, signals with the aid of a carry occurring from the most significant bit position of the displacement address part a page boundary crossing of the corresponding operand, characterized in that the address arithmetic unit consists of three sub-adding units, which are linked to one another as follows : a) a main address adder (AAD), forming the first sub-adding unit, is connected via a first and second input register (RA, RB) with associated first and second input multiplexer (MUX A, MUX B) on the one hand to a register set (RS), containing the base or index addresses (B1, B2, X2) of the individual operands, and on the other hand to an instruction buffer for feeding of the associated displacement address (D1, D2) ; b) as second sub-adding unit, a displacement/length adder (DL-ADD) is provided, to the two inputs of which the respectively associated displacement addresses (D1, D2) and operand lengths (L, L1, L2) are fed from the instruction buffer and the output of which is linked via a further input of the second input multiplexer (MUX B) to the second input register (RB) of the first sub-adding unit ; c) the third sub-adding unit is a field-length adder/subtracter (FE-ADD), which is connected by its first input to the output of the first sub-adding unit (AAD), to the second input of which the operand length (L, L1, L2) is fed from the instruction buffer and at the carry output of which a control signal (CY), occurring in the event of a page boundary crossing, can be picked off.
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