Slowly moving target-cancelling circuit for a Doppler radar

摘要

1. An elimination circuit for slow mobile echoes in a doppler radar system possessing a predetermined number of different recurrent frequencies and a predetermined passage time of the antenna beam to a target, said radar system comprising antenna receiving circuits (E1), said elimination circuit comprising - at least two doppler filters (FSx and FDy ) arranged to be connected with the receiving circuit, providing the values of two quadrature components of a detected signal, said doppler filters being followed by an envelope detector (DC) supplying, at an output connection (10), the digital value of the detected signal ; - a first switch (C1) possessing an input connected with the connection (10) of the envelope detector (DC) and a plurality of outputs (11 through 14) equal to the number of the different recurrent frequencies of the doppler radar system, said switch (C1) making it possible to connect its input with the output (11 through 14) corresponding to the instant recurrent frequency ; - summating registers (F1 through F4) functioning in a serial mode, connected with the outputs (11 through 14), each summating register having a length equal to that of the number of quanta distances of the radar system, and possessing an output at which it furnishes a value of the summating signal ; - a summating circuit (CS) connected at each output of the summating registers (F1 through F4) effecting a post-integration, during the passage time of the antenna beam to the target, of the detected signals in order to furnish an integration signal at one output, said output being connected with the first input of this output circuit (INH) ; - a coincidence circuit (ET and ET1) possessing as many inputs as there are recurrent frequency values, each of these inputs being connected with the output of one of the said summating registers (F1 through F4) in such a manner that the said coincidence circuit (ET1) furnishes a first incubation signal at an inhibition output when each summating register delivers a signal with a level above a predetermined threshold (S2) ; - an output circuit (INH) possessing at least one first input connected with the output of the summating circuit (CS) and a second input connected with the inhibition output of a logical gate of the AND type (ET2), said output circuit (INH) permitting, in the absence of a signal at its second input, the retransmission of every received signal at the second input, at one output to the display circuits, said circuit (INH) also permitting the disenablement of retransmission of any signal coming from the summating registers (F1 through F4) in the event of a signal being present at its second input ; - a control circuit (UC) furnishing signals to the switch (C1) and to the summating registers (F1 through F4) ; - devices for measuring the phase differences (vphi ni and DELTA vphi i ) of the detected signal between two recurrences, connected to the two doppler filters (FDx and FDy ) and furnishing at the input of a second switch (C3) a digital signal with the value of the said phase differences, the said switch (C3) possessing as many outputs (31 through 34) as there are values of the frequency of recurrence, each of the outputs being connected with a summating register (G1 through G4) of the said difference in phase, the outputs of the said summating registers (G1 through G4) further-more being connected with a maximum phase variation seek circuit (delta DELTA vphi ij ) whose output is connected with a threshold circuit (A3) furnishing at its output a second inhibition signal when the value of the signal at the output of the said maximum seek circuit is below a predetermined value, the said output of this threshold circuit (A3) being connected with a first input of the said logical gate of the AND type (ET2) of which a second input is connected with the inhibition output of the coincidence circuit (ET2) furnishing the first inhibition signal.